Eliminating access problems in assembly development

There are considerations in electronic assembly design which apply at the development phase for test points to be put in place by designers of printed circuit boards. New test technologies are helping overcome some of the barriers to access.


Test technology, JTAG/Boundary Scan, has become an increasingly valuable application for assembly testing at the design stage, in particular in the development departments of small and large companies. On the one hand this is due to the enormous potential the technology provides and, on the other hand, to the problems increasingly compact assemblies and components place on test technologies with respect to mechanical access.

Modern BGA packagings and high-speed transmission lines are looking for new approaches. Apart from the utilization opportunities provided by JTAG/Boundary Scan, there are additional benefits for designers?.

Questions are being asked whether the use of JTAG/Boundary Scan in development is really necessary. Is it not enough that designers – under consideration of some restrictions − must plaster their boards with test points? Must designers now write tests themselves? What is the return on this effort? To fully understand, a few things must be made clear.

Test generation

What is required for test generation? It is essential to know what component types are used, and how the component pins are interconnected. Each component type must be assigned to a related model. For example, there is a model for each Boundary Scan component describing the IC’s Boundary Scan structure, a so-called BSDL (Boundary Scan Description Language) model. Depending on the vendor, there are additional models describing non-Boundary Scan components such as RAM or driver ICs. But that is the only precondition to generate board tests.

The test system provides the models, and the required CAD data are limited to a net list and a component list. These can be found in the schematic that is usually available at an early board development stage. The advantage: problems that may occur in test generation can be solved easier, and test-depth-inconvenient designs can be changed extremely fast and simple. However, this is not all.

Generated tests are available already for the first prototypes. They can be tested with the same quality as the 0-series and finally the serial product – the same test depth, the same pin-level fault information. Now that the test bus necessary for Boundary Scan is available on the UUT (unit under test), e.g. via a connector, this interface can be used to load FPGA or CPLD components or to put the boot loader into the program flash. The resulting savings are apparent. But why are the designers to generate tests? These are test engineering tasks, including all associated problems.

However, there are a number of considerations to be taken into account here.

1. The designer knows the board best – starting with the component designations; where the focal points are; whether high test effort is justified; and design changes for test depth increase are quickly implemented – resulting in an assembly ideally designed for test. This all leads to efficient test generation and finally efficient testing.

2. The first prototype can already be tested by the same methods as the serial product. Therefore, the test depth is the same and the same pin-level fault information is provided. This leads to an efficient initiation of prototypes and 0-series under serial conditions.

3. Ideal interface for EMS – the test archive is simply passed to the EMS. The contract manufacturer doesn’t have to coordinate or balance test generation and test scope. Test changes are implemented rapidly.

For contract manufacturers, there is an extremely small amount of test effort (only the test equipment must be provided) leading to minimal costs. All in all, there are a significant number of advantages a designer benefits from to a large extent. That obviously compensates the manageable effort in test generation.

Standardized method

JTAG/Boundary Scan is the world’s only standardized electric test method (IEEE Std. 1149.x). Stimulating and measuring the single circuitries on assemblies is no longer executed via predetermined test points and its connected metrology, but rather Boundary Scan cells integrated into a component. The IC architecture is shown in image 1.

Necessary information transmission between test system and Boundary Scan component is executed via a standardized four-wire test bus. The test bus must be considered in board design, sort of replacing the test points that would have been determined for an In-Circuit Test (ICT) or Flying Probe Test (FPT). Consequently, a test system must only provide a port for this test bus

As test points are no longer required, there aren’t the same access problems as for ICT or FPT. Upon closer examination of image 1 it can clearly be seen that the Boundary Scan cells are located between the component’s pins and its inner logic. Hence, the core logic no longer plays a role for testing board circuitries. It doesn’t matter whether it is a processor or PLD.

How does a Boundary Scan test work? Image 2 is meant to illustrate this. First of all, a Boundary Scan component is switched to the external test mode (EXTEST). This is done by means of a signal interchange at Test Clock (TCK) and Test Mode Select (TMS) as well as setting a respective command via Test Data Input (TDI). From this moment on, the IC’s inner logic is separated from the pins. Now the Boundary Scan cell is exclusively responsible for the signal level at the component pin. Loaded with 1 or 0, a high level or low level is driven, respectively. Generally, at each pin there is a Boundary Scan cell for level measurement. It helps to verify test pattern and therefore check interconnections.


Boundary Scan − like any other test technology − requires design rules that must be considered. If such design rules are disregarded, the achievable test depth might be considerably affected or in extreme cases completely lost. Nothing is ‘sadder’ than a board that cannot be tested because of one missing interconnection. But there’s no need to worry about possibly ‘many’ design rules. Convenient software provides support for rule compliance. Moreover, it once again demonstrates that it makes sense to start with test generation at a very early stage of product design. Once the layout is finalized, things are relatively hard to change.

JTAG/Boundary Scan is  an efficient test method for digital components, in particular at the design stage it provides a number of advantages enabling completely new test approaches and previously unobtainable high quality. The following aspects are worth noting:

  • high-value test as early as the first prototype stage in series quality
  • in-system programming and test utilizing the same interface
  • ideal interface for EMS.

Compared to technological benefits, the requirements Boundary Scan puts on equipment, know-how and Design-for-Testability seem insignificantly small. With trends towards more and more compact packaging that restricts mechanical pin access and increasing integration density, there are technological benefits which outweigh the requirements put on equipment, know-how and design-for-testability.

By Mario Berger and Enrico Lusky, Goepel Electronics