Advanced electronic substrates for miniaturized applications

There is a strong desire to develop advanced packaging that can meet the growing demand for miniaturization, high-speed performance, and flexibility for handheld, portable, in vivo, and implantable devices. Tampering of electronic components is a twofold risk. First, sensitive health information stored on a device can be accessed and vital information for device operation can be altered. Secondly, replacement of components with counterfeit components can cause a device to malfunction or carry out malicious acts. Discussion surrounds the development of proven anti-counterfeit and product authentication solutions that can be incorporated into a variety of implantable or single use and disposable medical devices.

The wide range of applications for medical electronics drives unique requirements that can differ significantly from commercial & military electronics. To accomplish this, new packaging structures need to be able to integrate more dies with greater function, higher I/O counts, smaller die pad pitches, and high reliability, while being pushed into smaller and smaller footprints. As a result, the microelectronics industry is moving toward alternative, innovative approaches as solutions for squeezing more function into smaller packages. In the present report, key enablers for achieving reduction in size, weight, and power (SWaP) in electronic packaging for a variety of medical applications are discussed. These enablers include materials selection, embedded passives, System-in-Package (SiP), flex and rigid-flex circuits. Manufacturing methods and materials for producing advanced organic substrates and flex along with ultra fine pitch assemblies are discussed along with descriptions of novel anti-counterfeiting approaches for the fabrication of medical devices. A variety of nano-micro composite based signature materials well suited for electronic packaging applications have been developed. These materials enable verification of authenticity with excellent control of signature properties. The World Health Organization (WHO) has identified counterfeiting to be a major risk to the medical device industry. Reports such as those published by the International Medical Products Anti-Counterfeiting Taskforce (IMPACT) identify and discuss in detail some of the issues involved.


Flexible technologies are important at all levels of microelectronics due to their desired properties, bend radius, and ability to fit within the system housing. The classification of flex is varying with its rapidly growing technological significance in electronics. Continuous technological growth and application of new complex structures are forcing changes in the limits placed on the term of ‘classical flex’. Now flex defines the technology relating to any bendable or stretchable structures or devices. The performance of flex is primarily determined by its bend radius. The final structure bend radius solely depends on dielectric layer (composition, thickness), circuit design, and number of layers. Most of the miniaturized SWaP (size, weight and power) reduction applications use high density flex circuits due to their flexibility, reduced weight, and space savings. For example, flexible solar cells, displays, and sensors typically use high density flex substrates. Multi-layer rigid structures can be converted into single or double layer high density flex structures and open up new directions for SWaP reduction in next generation technology applications.

Current flex technology is capable of fabricating a variety of flex devices by utilizing thin or ultra-thin polyimide flex material and the fine line circuitization required for SWaP reduction. Circuitized solder dams help to prevent solder bridging during flip chip assembly, and is key for use of bare die in fine pitch applications. Fine line circuitization was achieved using a semi-additive, or pattern plating, process. Figure 1 illustrates SEM micrographs and a photograph of a cross section of a double-sided high density flexible substrate. Line width and spacing between lines of 11 μm are defined using a semi-additive plating process to produce metal layers having thickness of 2 to 10 μm. Vias having diameters of 25 to 50 μm are drilled through the polyimide film using a frequency-tripled Nd-YAG laser, and subsequently plated using the semi-additive plating process. The circuitized flex substrate was coated with flexible soldermask, 6-10 μm thick, on both sides of the substrate, prior to placement of die and/or other surface mounted components on the flex.

A variety of double-layer flex substrates can be laminated together with a joining layer and subsequently drilled and plated to achieve electrical interconnection between adjacent flex substrates. Each flex can have signal, voltage, and ground planes. It is also possible to use signal, voltage, and ground features on the same plane. As a case study, 6 double layer flexes were used together with joining layers to fabricate multilayer flex substrates. Two basic building blocks are used for this case study. One is a double layer flex and the second building block is a joining layer. By alternating flex and joining layer in the stackup one can fabricate multilayer structure. A six metal layer structure with six single-sided flex substrates, each having thickness of 12.5 μm and five joining layers each having thikness of 25 μm, is shown in Figure 2. Total thickness of laminated multilayer flex is about 190 μm. A similar approach with double-sided flex substrates would yield a package having 12 metal layers without an appreciable increase in total laminate thickness. The current process can be used to fabricate a wide range of multilayer substrates with joining layer having PTH diameters in the range of 50 to 150 μm.


Some system-in-Package (SiP) designs eliminate packaged die by directly attaching the bare die to the SiP with finer pitch flip chip technology [3]. Additionally, the area used for surface mount passive components can be greatly reduced by embedding many of the capacitors and resistors into the substrate. Thinner, high-density interconnect substrate technologies with lower inductance, minimize the need for decoupling capacitors in the design. In some cases, the Printed Wiring Board (PWB) connector systems that consume large amounts of space in the board assembly can be reduced with a small pitch connector system. The overall approach is able to covert a large PWB assembly into a much smaller SiP with the full surface area on both sides of the substrate effectively utilized to mount active and passive components. For example, a high-density interconnect and embedded passive-based substrate technology combined with smaller bare die and component body sizes have been shown to result in approximately 27 times physical size reduction for existing printed wiring board assemblies, with considerable reductions in weight and power consumption (Figure 3). Reduced interconnect lengths and corresponding load is responsible for power consumption reduction. Shorter interconnect length further reduces or eliminates the need for termination resistors for some net topologies. The SiP designs can be implemented on various package levels depending on the application requirements including full systems, functional modules, MEMS sensor related packaging, and component obsolescence issues.

High density

A key technology to achieve SWaP reduction for electronics is the substrate capability to sweep components off the surface and embed them into the stack-ups. Advanced high density interconnect (HDI) features, including thin core or coreless stack-ups, small drill hole diameter, and fine feature circuitry, are required to support these flip chip components and maximize the SWaP reduction for a given assembly. Optimized wireability is achieved when dense circuitization capability (e.g., < 25 um L/S) is paired with laser drilled vias having diameters in the range of 50 um. The smaller via diameter minimizes capture pad area requirements and results in a much greater via density for substrate size reduction as compared to conventional technology. The absence of glass cloth in the dielectric generates a smoother dielectric surface finish suitable for high resolution photolithography for higher wiring density. Omission of glass cloth substantially reduces the dielectric layer thickness less for achieving much thinner stack-ups. Figure 4 shows a wirebondable miniaturized organic substrate for implantable cardiac devices such as implantable cardioverter defibrillators (ICDs) and pacemakers. A Z-axis interconnect approach is another way to achieve HDI substrates. Specifically, metal-to-metal z-axis electrical interconnection [2] among the cores of varying size or among flexible and rigid elements (rigid-flex), to form a single HDI structure is described.

The structure employs an electrically conductive medium to interconnect thin cores. The cores are built in parallel, aligned, and laminated to form a variety of multilayer high density structures including rigid, rigid-rigid, rigid-flex, stacked packages, or RF substrates. Thin film resistor material can provide individual miniaturized resistors with areas as small as 0.2 mm2. Laser trimming can produce tight tolerance resistors that possess nearly equivalent tolerance to those available in SMT packages. High Dk nanomaterials and active devices are incorporated into the stack-up to provide embedded capacitance and embedded actives, respectively. HDI substrate technology, component footprint reduction, and ability to assemble miniaturized components on dense substrates are important for significant SWaP reduction.

Package-interposer-package (PIP) 

Package-Interposer-Package (PIP) is a 3D integration approach used for combining multiple substrates, stacked die, stacked packaged die, etc., into a single package. PIP also favors high density, complex, system integration by choosing appropriate substrate design and interconnects management. Re-workable solder-based interconnects were used for electrical interconnection between the packages. Traditional Package on Package (PoP) approaches use direct solder connections between the substrates and preclude (or limit) the use of stacked die on the bottom substrate, in order to reduce the distance between the packages to achieve finer pitch. Increasing the number of dies attached to the bottom package will increase the distance between the packages and hence will require larger solder balls to connect the packages. Larger solder ball will increase the overall package pitch. For PIP, the stability imparted by the interposer eliminates stiffener requirements, results in less warpage, reduces interconnect distance, and allows assemblers of the PIP to select the top and bottom components (substrates, die and stacked TSV die, modules) from various suppliers. This mitigates the problem associated with the warpage variation trends from room temperature to reflow temperature for different materials/processes/ substrates/modules when combined with other packages. PIP is suitable for more space-efficient designs, and can accommodate any stacked die height on the bottom package without compromising warpage and stability. PIP can accommodate organic, ceramic, or silicon modules with single or stacked assembled die, where each module or die can be detached and replaced without affecting the rest of the construction. PIP can also accommodate heterogeneous technologies including 2D and 2.5 D technology. PIP will be appropriate for expensive high-end electronics, since a damaged, non-factional part of the package can be selectively removed and replaced. A Package-Interposer-Package (PIP) test vehicle was fabricated by alternating four packages and three interposers in the lay-up and joining them together with solder using a reflow process. PIP requires at least (n-1) number of interposers for n number of packages. Figure 5 shows extended PIP structures for connecting four (n) packages with three (n-1) interposers using solder-based interconnection. An optical photo of the extended PIP structure is shown in Figure 6.

3D Integration SiP

The miniaturized SiP with its reduced substrate size having embedded passives provides a high wireability package with excellent communication from top to bottom and facilitates double side assembly approach. When converting larger PCBs to miniaturized SiP assemblies, there may be issues with insufficient space to accommodate all the components. In the present paper, a multiple SiP approach is applied to accommodate all the components, and interposers are used in a 3D-integration of these multiple SiP to provide a SiP-Interposer-SiP construction, an unique solution for next generation complex packaging. Figure 7 and Figure 8 represent two high-density double-sided assembled circular SiP substrates attached with each other using an interposer to produce a 3D SiP-Interposer-SiP construction. PIP construction using various miniaturized assembled packages (SiP) can be attached to a board to generate 3D architecture. The 3D integration method can be used to attach, repair, or upgrade individual assembled packages (SiP) in the stack. Figure 8 shows a PIP concept of breaking a complex expensive high-end electronic structure into SiP-interposer-SiP prior to attach to a low end board construction.


There are novel anti-counterfeiting approaches for the fabrication of advanced packaging with several anti-counterfeit signature approaches possible, but applying them to the manufacturing environment is critical. The manufacturing environment requires faster and cheaper ways to detect the components. Furthermore, processing cost of anti-counterfeit signatures sometimes limits their application. Fabrication of advanced packaging with parts authentication technologies such as embedded signature circuits with zero cost adders and signature nano or micro materials possess these desired attributes of anti-counterfeit measures.

Increased functionality

Miniaturization of electronic devices are driving the packaging need for achieving increased functionality with decreasing size, weight and power (SWaP). Advanced substrate technology with novel interconnection cross sections, embedded passives and actives, and 3D integration solutions have been successfully implemented to reduce electronics volume and advance the capabilities of electronic device technology. For advanced flex and rigid-flex circuit constructions, high resolution photolithography and semi-additive plating processes, are important to achieve higher wiring density with the fine line circuitry required for ultra fine pitch flip chip assembly. A PIP approach was developed for 3D integration of various system-in-package (SiP) constructions.